微机verilog课件张伟lec01_v3.pptxVIP

Microcomputer Principle and Interfacing Techniques微机原理与接口技术 ;FPGA for FUN!;Outline;Objective;Hardware Developing;New Hardware Developing Solution;Music Box;Requirement;Hardware Design: Schematic for Music Box;The HDL design;Part 1: Simple Beep;FPGAs can easily implement binary counters. For example, a 16-bit counter is going to count from 0 to 65535 (65536 different values). Assuming we have a 25MHz clock available and the counter is free running, the highest bit of the counter toggles at a frequency of65536=381Hz.The Verilog HDL code looks like this:;;A note (440Hz);Problem The