EDA技术应用7.2.4xilinx原版课件VHDL语言.ppt

PROGRAMMABLE LOGIC DESIGN WITH VHDLEric Deng ( hai tao )Field Applications EngineerCypress Semiconductoredx@ Objectives You will learn enough about VHDL to: Design efficient combinatorial and sequential logic Design state machines and understand implementation trade-offs Design using multi-level hierarchy Identify how VHDL will synthesize and fit into a PLD or CPLD Objectives (contd.) You will learn enough about the Warp software to: Compile and synthesize VHDL designs for programmable logic devices Target PLDs/CPLDs Simulate the resulting device functionality in Nova Use the report file to determine operating frequency, set-up time, clock to output delay, and device resource usage. Agenda VHDL Design Descriptions The Entity, Ports, Modes, Types Exercise #1 The Architecture, Architecture Styles VHDL Statements, Combinatorial Logic Processes, Signals Vs. Variables VHDL Operators/Overloading/Inferencing VHDL Identifiers Exercise #2 MORNING BREAK Using Warp Exercise #3 Registered Logic Implicit Memory LUNCH Exercise #4 State Machines and State Encoding Exercise #5 AFTERNOON BREAK Hierarchical Designs Exercise #6 Miscellaneous Topics Summary and Conclusion What is VHDL ? V HSIC (Very High Speed Integrated Circuit) Hardware Description Language VHDL is a Design Description Language VHDL is a Design Documentation Language VHDL is a Simulation Language It is an IEEE Standard Language (IEEE1076 1164) Why Use VHDL? Very Fast Time-to-Market Allows designers to quickly develop designs requiring tens of thousands of logic gates or more Provides powerful high-level constructs for describing complex logic Supports modular design methodology and multiple levels of hierarchy One language for design and simulation Allows creation of device-independent designs that are portable to multiple PLD vendors Allows user to pick any synthesis tool, vendor, or device VHDL Design Descriptions VHDL design descriptions consist of an ENTITY declaration and an ARCHITECTURE b