超大规模集成电路第九次作业秋段成华.docx

精品文档 精品文档 袄 莀肇 薀虿 蚈莂 芄薄 肂羇 艿袀 螈羄 蚅膃 蒀袇 肈膁 袈膂 肆PAGE PAGE24 精品文档 PAGE 超大规模集成电路第九次作业 2016秋-段成华 Assignment9 Designan8-bitupanddownsynchronouscounterinVHDLwiththefollowingfeatures: Thesameportsareusedforsignalstobeinputtedandoutputted.Theportsarebi-directionallybuffered(three-state). Thecounteriswithanasynchronousresetthatassignsaspecificinitialvalueforcounting. Thecounteriswithasynchronousdataloadcontrolinputforanewvalueofcountingandanenablecontrolinputforallowingtheupanddowncounting.Theloadcontrolinputhasapriorityovertheenablecontrolinput.Thisimpliesthatwhentheloadoperationisinprocessthecounteroperationisprohibited. Somedatatypes,suchasSTD_LOGIC,UNSIGNED,SIGNEDandINTEGER,maybeused. Synthesizethedesign.Createasetofreasonableinputwaveformsforyourdesignandcompletebothbehavioralandpost-placeroutesimulationswithinternalsignalsand/orvariablesincludedinwaveformorlistwindows. Solution:代码如下： libraryIEEE; useIEEE.STD_LOGIC_1164.ALL; useIEEE.STD_LOGIC_ARITH.ALL; useIEEE.STD_LOGIC_UNSIGNED.ALL; Uncommentthefollowinglibrarydeclarationifinstantiating anyXilinxprimitivesinthiscode. --libraryUNISIM; --useUNISIM.VComponents.all; entitycount_8_bidiris cnt_out=(others=0); elsif rising_edge(clk)then if(load=1)then cnt_out=cnt_in; elsif(enable=1)then cnt_out=cnt_out+1; else cnt_out=cnt_out-1; endif; endif; endprocess; endBehavioral; 解释代码：这里有两个进程，进程0时是用来控制三态门控制的双向端口。当cnt作为输入时（load=1），把cnt赋给cnt_in（初值装载），然后置cnt为高阻状态；否则，即cnt作为输出时（load=0），把cnt_out（计数器计数输出值）赋给cnt。进程1的作用是：当复位信号rst=1，计数器输出cnt_out为全0，否则在时钟的上升沿检测cnt端口是作为输入还是作为输出，当作为输入时 load=1），把cnt_in中的数取进来，然后当up_down=0时，进行加法运算，否则做减法运算，同时可以和进程0配合当load=0，将数值从cnt_out输出到 cnt。 TestBench代码： LIBRARYieee; USEieee.std_logic_1164.ALL; USEieee.std_logic_unsigned.all; USEieee.numeric_std.ALL; ENTITYcount_8_bidir_tbIS ENDcount_8_bidir_tb; ARCHITECTUREbehaviorOFcount_8_bidir_tbIS ComponentDeclarationfortheUnitUnderTest(UUT)COMPONENTcount_8_bidir PORT( oe:INstd_logic; clk:INstd_logic; rst:INstd_logic; load:INstd_logic; enable:IN std_logic; cnt:INOUT std_logic_vec