EDA数字时钟课程设计.pptVIP

EDA数字时钟课程设计总结 数字时钟设计顶层文件 数字时钟引脚图 数字时钟设计模块 1、秒计时器模块 2、分计数器模块 3、小时计数器模块 4、报警模块 5、时间数据扫描分时选择模块 6、译码器模块 7、数字时钟实物演示 秒计数器模块 分计数器模块 小时计数器模块 报警模块 时间数据扫描分时选择模块 译码器模块 秒计数器 LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY second IS PORT( clk,reset,setmin:IN STD_LOGIC; enmin:OUT STD_LOGIC; daout:out std_logic_vector(6 downto 0)); END entity second; ARCHITECTURE fun OF second IS SIGNAL count:STD_LOGIC_VECTOR(6 downto 0); SIGNAL enmin_1,enmin_2:STD_LOGIC; BEGIN daout=count; enmin_2=(setmin and clk); enmin=(enmin_1 or enmin_2); process(clk,reset,setmin) begin if(reset=0) then count=0000000; elsif(clkevent and clk=1)then if(count(3 downto 0)=1001)then if(count16#60#)then if(count=1011001)then enmin_1=1; count=0000000; else count=count+7; end if; else count=0000000; end if; elsif(count16#60#)then count=count+1; enmin_1=0 after 100 ns; else count=0000000; end if; end if; end process; end fun; 分计数器 LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY minute IS PORT( clk,clk1,reset,sethour:IN STD_LOGIC; enhour:OUT STD_LOGIC; daout:out std_logic_vector(6 downto 0)); END entity minute; ARCHITECTURE fun OF minute IS SIGNAL count:STD_LOGIC_VECTOR(6 downto 0); SIGNAL enhour_1,enhour_2:STD_LOGIC; BEGIN daout=count; enhour_2=(sethour and clk1); enhour=(enhour_1 or enhour_2); process(clk,reset,sethour) begin if(reset=0)then count=0000000; elsif(clkevent and clk=1)then if(count(3 downto 0)=1001)then if(count16#60#)then if(count=1011001)then enhour_1=1; count=0000000; ELSE count=count+7; end if; else count=0000000; end if; elsif(count16#60#)then count=count+1; enhour_1=0after 100 ns; else count=0000000; end if; end if; end process; END fun; 小时计数器 LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY hour IS PORT( clk,reset:IN STD_LOGIC; daout:out std_logic_vector(5 downto 0)); END entity hour; ARCHITECTURE fun OF hour IS S