Timing Analysis Overview 用户使用指南.pdf

Timing Analysis Overview 6 2014.06.30 QII53030 Subscribe Send Feedback Timing Analysis Overview Comprehensive static timing analysis involves analysis of register-to-register, I/O, and asynchronous reset paths. Timing analysis with the TimeQuest Timing Analyzer uses data required times, data arrival times, and clock arrival times to verify circuit performance and detect possible timing violations. The TimeQuest analyzer determines the timing relationships that must be met for the design to correctly function, and checks arrival times against required times to verify timing. This chapter is an overview of the concepts you need to know to analyze your designs with the TimeQuest analyzer. Related Information The Quartus II TimeQuest Timing Analyzer For more information about the TimeQuest analyzer flow and TimeQuest examples. TimeQuest Terminology and Concepts Table 6-1: TimeQuest Analyzer Terminology Term Definition nodes Most basic timing netlist unit. Used to represent ports, pins, and registers. cells Look-up tables (LUT), registers, digital signal processing (DSP) blocks, memory blocks, input/output elements, and so on. (1) pins Inputs or outputs of cells. nets Connections between pins. ports Top-level module inputs or outputs; for example, device pins. clocks Abstract objects representing clock domains inside or outside of your design. Notes: