EDA技术应用3.2.2元器件手册ECP3Datasheet.pdfVIP

LatticeECP3 Family Data Sheet DS1021 Version 01.7EA, December 2010 LatticeECP3 Family Data Sheet Introduction December 2010 Data Sheet DS1021 Features • Dedicated read/write levelling functionality • Dedicated gearing logic  Higher Logic Density for Increased System • Source synchronous standards support Integration – ADC/DAC, 7:1 LVDS, XGMII • 17K to 149K LUTs – High Speed ADC/DAC devices • 133 to 586 I/Os • Dedicated DDR/DDR2/DDR3 memory with DQS  Embedded SERDES support • 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit • Optional Inter-Symbol Interference (ISI)  SERDES, and 8-bit SERDES modes correction on outputs • Data Rates 230 Mbps to 3.2 Gbps per channel  Programmable sysI/O™ Buffer Supports for all other protocols Wide Range of Interfaces • Up to 16 channels per device: PCI Express, • On-chip termination SONET/SDH, Ethernet (1GbE, SGMII, XAUI), • Optional equalization filter on inputs CPRI, SMPTE 3G an