verilog数字时钟源程序,分频模块,计时模块,子函数调用,及测试模块.pdfVIP

分频 module clkgen (clock,reset,clkdiv,clk500); input clock,reset; output clkdiv; output clk500; reg [31:0] counter1; reg clkdiv; reg clk500; reg [31:0] counter0; /********??1HZ?????*********/ always@(posedge clock) if(reset) begin clkdiv=0; counter0=0; end else if(counter0==24d4) begin counter0=0; clkdiv=~clkdiv; end else begin counter0=counter0+1; clkdiv=clkdiv; e