数字集成系统设计课程第四章参考highspeedfifo.pptxVIP

4.4 Design Example: High Speed FIFOs in Spartan-II FPGA4.4.1 LFSR (Linear Feedback Shift-Register) CounterUsing Linear Feedback Shift-Register (LFSR) counters to address the RAM makes the design even simpler. For a 4-bit counter, the basic XNOR feedback from Q3 and Q4 would exclude the all-ones state. By decoding the two states where the lower three bits are all ones, and inverting the feedback for those states, the 4-bit LFSR counter counts modulo 16, and has no lock-up state. Divide-by 5 to 16 Counter: Feedback for modulo 16: D1 = (Q3 XNOR Q4) XOR (Q1 AND Q2 AND Q3) Counters with a short c