Xilinx_Design_Reuse_Methodology设计使用手册.pdfVIP

Xilinx Design Reuse Methodology for ASIC and FPGA Designers SYSTEM-ON-A-CHIP DESIGNS REUSE SOLUTIONS Xilinx An Addendum to the: REUSE METHODOLOGY MANUAL FOR SYSTEM-ON-A-CHIP DESIGNS 2 Table of Contents 1 Introduction 3 1.1 System-on-a-Reprogrammable Chip 3 1.2 Why Use an FPGA?4 1.2.1 ASIC vs. FPGA Design Flows 4 1.3 A Common Design Reuse Strategy 6 2 System Level Reuse Issues for FPGA