Quartus常见警告和错误借鉴.pdfVIP

Quartus 常见警告和错误 1 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list 没把 singal 放到 process （）中 2 Warning: Found pins ing as undefined clocks and/or memory enables Info: Assuming node CLK is an undefined clock -= 可能是说设计中产生的触发器没有使能端 3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object clk_scan of mode out cannot be read. Change object mode to buffer or inout. 信号类型设置不对， out 当作 buffer 来定义 4 Error: Node instance clk_gen1 instantiates undefined entity clk_gen 引用的例化元件未定义