[数字电路 西电]数字系统设计举例 - VHDL设计初步习题解.pdfVIP

习题 10 10-1 试用VHDL 描述一个一位全加器电路。 解：程序设计如下： library ieee; use ieee.std_logic_1164.all; entity my_adder is port ( a,b,cin : in bit; cout,sum : out bit ); end my_adder; architecture behave of my_adder is begin sum = a xor b xor cin; cout = ((a xor b) and cin) or (a and b); end behave; 10-2 试编写两个四位二进制相减的VHDL 程序。 解：程序设计如下： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity my_sub4 is port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); ci : in std_logic; co : out std_logic; result : out std_logic_vector(3 downto 0) 1 ); end my_sub4; architecture behave of my_sub4 is signal s: std_logic_vector(4 downto 0); begin s = (0a )+(0b)+(0000ci); result = s(3 downto 0); co = s(4); end behave; 10-3 试用VHDL 描述一个 3-8 译码器。 解：程序设计如下： library ieee; use ieee.std_logic_1164.all; entity my_3to8decoder is port ( e1,e2,e3 : in std_logic; a : in std_logic_vector(2 downto 0); y : out std_logic_vector(7 downto 0) ); end my_3to8decoder; architecture behave of my_3to8decoder is begin process(a) begin if (e1=’1’ and e2= ’0’ and e3= ’0’) then case a is when 000 =y = when 001 = y= when 010 = y = when 011 = y = when 100 = y = when 101 = y = when 110 = y = when 111 = y = when others = y = null;