TECHNOLOGY GS8322V18(B E) GS8322V36(B E) GS8322V72(C) 2M x 18 1M x 36 512K x 72 36Mb S DCD Sync Burst SRAMs 250 MHz 133 MHz 1.8 V VDD 1.8 V I O说明书用户手册.PDF

查询GS8322V18GB-133供应商 Preliminary GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C) 119-, 165-, 209-Pin BGA 2M x 18, 1M x 36, 512K x 72 250 MHz–133 MHz Commercial Temp 1.8 V VDD Industrial Temp 36Mb S/DCD Sync Burst SRAMs 1.8 V I/O Features either linear or interleave order with the Linear Burst Order (LBO) • FT pin for user-configurable flow through or pipeline operation input. The Burst function need not be used. New addresses can be • Single/Dual Cycle Deselect selectable loaded on every cycle with no degradation of chip performance. • IEEE 1149.1 JTAG-compatible Boundary Scan Flow Through/Pipeline Reads • ZQ mode pin for user-selectable high/low output drive The function of the Data Output register can be controlled by the • 1.8 V +10%/–10% core power supply user via the FT mode . Holding the FT mode pin low places the • 1.8 V +10%/–10% core power supply RAM in Flow Through mode, causing output data to bypass the • 1.8 V I/O supply Data Output Register. Holding FT high places the RAM in • LBO pin for Linear or Interleaved Burst mode Pipeline mode, activating the risi