IDT 256K x 36 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I O Burst Counter Pipelined Outputs IDT71V65602 IDT71V65802说明书用户手册.PDF

查询IDT71V65602供应商 256K x 36, 512K x 18 IDT71V65602 3.3V Synchronous ZBT™ SRAMs IDT71V65802 2.5V I/O, Burst Counter Pipelined Outputs Address and control signals are applied to the SRAM during one clock 256K x 36, 512K x 18 memory configurations cycle, and two cycles later the associated data cycle occurs, be it read or write. Supports high performance system speed - 150MHz The IDT71V65602/5802 contain data I/O, address and control signal (3.8ns Clock-to-Data Access) registers. Output enable is the only asynchronous signal and can be used to TM ZBT Feature - No dead cycles between write and read cycles disable the outputs at any given time. Internally synchronized output buffer enable eliminates the A Clock Enable () pin allows operation of the IDT71V65602/5802 to be suspended as long as necessary. All synchronous inputs are ignored need to control when () is high and the internal device registers will hold their previous Single R/ (READ/WRITE) control pin Positive clock-edge triggered address, data, and control values. signal registers for fully pipelined applications There are three chip enable pins (1, CE2, 2) that allow the 4-word burst capability (interleaved or linear) user to deselect the device when desired. If any one of these three are not asserted when ADV/ is low, no new memory operati