CYPRESS CY7C1370DV25 CY7C1372DV25 18-Mbit (512K x 36 1M x 18) Pipelined SRAM with NoBL™ Architecture 数据手册说明书.PDF

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CYPRESS CY7C1370DV25 CY7C1372DV25 18-Mbit (512K x 36 1M x 18) Pipelined SRAM with NoBL™ Architecture 数据手册说明书.PDF

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查询CY7C1370DV25供应商 CY7C1370DV25 CY7C1372DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x • Supports 250-MHz bus operations with zero wait states 36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are — Available speed grades are 250, 200 and 167 MHz designed to support unlimited true back-to-back Read/Write • Internally self-timed output buffer control to eliminate operations with no wait states. The CY7C1370DV25 and the need to use asynchronous OE CY7C1372DV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with • Fully registered (inputs and outputs) for pipelined