数电顶层设计程序.docxVIP

分频器： module fenpin25(clk,rst,clk_1hz); input clk; input rst; output clk_1hz; reg clk_1hz; reg [23:0] cnt; always@(posedge clk or posedge rst) begin if(rst==1b1) cnt=24d0; else if(cnt=begin cnt=24d0; clk_1hz=~clk_1hz; end else cnt=cnt+1; end endmodule 十进制计数器： module cnt10(rst,clk,cnt,load); input rst,clk, load; output [3:0] cnt; input [3:0]d; reg [3:0] cnt; always@(posedge clk) begin if( load) cnt=d; else if(!rst) cnt=4b000; else if(cnt==4d9) cnt=4b000; else cnt=cnt+1; end endmodule module qiduan(cnt,led,scan); input [3:0] cnt; output [6:0] led; output [3:0]