数电模拟程序.docxVIP

module miaomaichong( input wire clr, input wire clk, ); reg[3:0] z3; reg[2:0] z1,z2; reg [23:0] q1; always@(posedge clk ) begin q1=q1+1; end assign mclk=q1[23]; always@(posedge mclk or posedge clr) begin if(clr==1) begin z1=0; z2=0; z3=0; end else begin if(z1==2) z1=0; else z1=z1+1; if(z2==5) z2=0; else z2=z2+1; if(z3==8) z3=0; else z3=z3+1; end end endmodule 约束文件： NET clk LOC=B8; NET clr LOC=P11; NET z1[2] LOC=G1; NET z2[2] LOC=P4; NET z3[3] LOC=N4; module jixunqi( input wire load, input wire clk, input wire clr, input wire[3:0] d, output reg[3:0] q ); reg [27:0]q1; alway