cpu电子科技大学.docxVIP

module MUX32_2_1( input [31:0] A, input [31:0] B, input Sel, output[31:0] O ); assign O = Sel? B : A; endmodule module MUX32_4_1( input [31:0] A, input [31:0] B, input [31:0] C, input [31:0] D, input [1:0] Sel, output[31:0] O ); assign O = (Sel == 2b00)? A : (Sel == 2b01)? B : (Sel == 2b10)? C : D; Endmodule module MUX5_2_1( input [4:0] A, input [4:0] B, input Sel, output[4:0] O ); assign O = Sel? B : A; Endmodule module dff32( input [31:0] D, input Clock, input Reset, output reg [31:0] Q ); a