verilog程序60进制计数器.docxVIP

module count60_dongtai_LED ( input clk, input rest_n, output reg [2:0] sel, //位选output reg [6:0] display ); reg [15:0] count_clk; // 分频计数器，最大 2^16=64K 分频 reg [5:0] sum_num; //计数缓存器,2^6=64 reg [3:0] g_bit; //个位 reg [3:0] s_bit; //十位reg [3:0] disp_temp; //分频 always @ (posedge clk or negedge rest_n) begin if(rest_n ==0) begin count_clk=16b0; end else begin if(count_clk==16hffff) begin count_clk=16b0; end else begin count_clk=count_clk+1b1; end end end // 60 进制计数 always @ (negedge count_clk[3] or negedge rest_n) begin if(rest_n ==0) begin g_bit=4b0; s_bit=4b0; sum_num=6b0; end else begin if (sum_n