常用芯片资料——NE_SA_SE555_C_2.pdfVIP

NE/SA/SE555/SE555C Timer Product data 2003 Feb 14 Supersedes data of 1994 Aug 31 Timer NE/SA/SE555/SE555C DESCRIPTION PIN CONFIGURATION The 555 monolithic timing circuit is a highly stable controller capable of producing accurate time delays, or oscillation. In the time delay D and N Packages mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the GND 1 8 VCC free running frequency and the duty cycle are both accurately TRIGGER 2 7 DISCHARGE controlled with two external resistors and one capacitor. The circuit OUTPUT 3 6 THRESHOLD may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200 mA. RESET 4 5 CONTROL VOLTAGE SL00349 FEATURES • Turn-off time less than 2 µs Figure 1. Pin configuration • Max. operating frequency greater than 500 kHz BLOCK DIAGRAM • Timing from microseconds to hours • Operates in both astable and monostable modes VCC