verilog hdl高级数字设计源码addvb models.pdfVIP

specify // Module paths specparam Area_Cost = 4268.16; (negedge CLK2 = (Q +: DATA1)) = (0.525:1.129:2.889, 0.749:1.525:3.948); specparam RiseScale$CLK2$Q = 0.00094:0.00205:0.00540; specparam FallScale$CLK2$Q = 0.00086:0