用VHDL语言设计基本逻辑电路.pptVIP

architecturertlofdff1isbeginprocess(clk)beginifclk=1thenq=d;endif;endprocess;endrtl;－－电平触发还是边沿触发？－－若改为process(clk,d),电平触发还是边沿触发？libraryieee;useieee.std_logic_1164.all;entitydff2isport(d,clk:instd_logic;f.e.201enddff2;q:outstd_logic);02architecturertlofdff2is1begin2process3begin4waituntilclkeventandclk=1;5q=d;6endprocess;7endrtl;8GatedDLatchwithAsynchronousClear非同步复位的D锁存器与一般的D锁存器相比多了一个复位输入端clr。当clr=‘0’时，输出被强制复位。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYdffrISPORT(d,clk,clr:INSTD_LOGIC;f.e.101ENDdffr;q:OUTSTD_LOGIC);02ARCHITECTURErtlOFdffrISBEGINPROCESS(clk,clr)BEGINIFclr=0THENq=0;ELSIFclkEVENTandclk=1THENq=d;ENDIF;ENDPROCESS;ENDrtl;DFFwithasynchronousclear:PROCESS(clk)BEGINIFclkEVENTandclk=1THENIFclr=‘0’THENq=0;ELSEq=d;ENDIF;ENDIF;ENDPROCESS;Ex:WritetheVHDLcodesforaDFFwithasynchronousclearandpreset.Note:presetispriorityofclear.2、JKFlip-FlopLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;f.e.1PORT(clk,clr,pset,j,k:INSTD_LOGIC;qb,q:OUTSTD_LOGIC);ENDjkff1;ARCHITECTURErtlOFjkff1ISSIGNALqs,qbs:STD_LOGIC;ENTITYjkff1ISPROCESS(j,k,clk,clr,pset)BEGINBEGINIFpset=0THENqs=1;qbs=0;ELSIFclr=0THENqs=0;qbs=1;ELSIFclkEVENTandclk=1THENIFj=0ANDk=1THENqs=0;qbs=1;ELSIFj=1ANDk=0THENqs=1;qbs=0;ELSIFj=1ANDk=1THENqs=NOTqs;qbs=NOTqbs;ENDIF;ENDIF;ENDPROCESS;q=qs;qb=qbs;ENDrtl;Question:Iftheclearandpresetareactivesimultaneously,what’stheresult?126543IFpset=0ANDclr=1THENqs=1;qbs=0;ELSIFclr=0ANDpset=‘1THENqs=0;qbs=1;..1