FP设计中ChipScope Pro调试与验证应用.pptx

ThismaterialexemptperDepartmentofCommercelicenseexceptionTSUXilinxOn-ChipDebugUsingChipScopePro

ChipScopePro2Aftercompletingthismodule,youwillbeableto:ObjectivesStatehowtheChipScopeProAnalyzerfacilitatehardwaredebuggingListvariousavailableChipScopeProAnalyzercoresandtheirfunctionality

ChipScopePro3OutlineIntroductionDebuggingUsingChipScopeProInsertingChipScopeCoreSummaryLab6:ChipScopeProLab

ChipScopePro4DebugandVerificationisCriticalDebugandverificationcanaccountforover40%ofanFPGAdesigntimeSerialnatureofdebugandverificationcanmakeitdifficulttooptimizeInefficientstrategymayresultinproductlaunchdelayLossinmarketshareLossoffirst-to-marketadvantagesFinalDeviceDesignImplementationDesignSpecification40%ofDesignTimeDesignVerificationandDebug

ChipScopePro5TraditionalDebugLimitedInternalVisibilityHowdoIaccesstheembeddedsystembus…HardIPCoresCan’tgetinternalaccessto…FullScanInsertionIncreasesoverhead…It’sTooLateAnyway!Re-spinsareENORMOUSLYexpensiveCo-VerificationToolsarecumbersomeandslowModelingissuesIOPadsIOPadsIOPadsIOPadsLogicBISTMemoryBISTAccessMemoryArrayCPUCoreIPCoreCustomBoundaryScanTAPControllerEmbeddedSystemBusCustomLogicCustomCoreChallengesaccessinginternalsignals

ChipScopePro6TraditionalDebug

Dedicatedpinsconnectedtologicanalyzer

ExternalLogicAnalyzerPinsVirtex-IIProXC2VP20FF1152ProbepointsRequiresExtensiveDedicatedI/OforDebugDrivingsignalstoexternalI/OintroducesadditionalproblemsInflexiblesolutionDifficultorimpossibletoaddadditionaldebugpinsifneededLimitedvisibilitytoon-chipactivity

ChipScopePro7OutlineIntroductionDebuggingUsingChipScopeProInsertingChipScopeCoreSummaryLab6:ChipScopeProLab

ChipScopePro8ChipscopeDebugIOPadsIOPadsIOPadsIOPadsBoundaryScanTAPControllerEmbeddedSystemBusMemoryArrayPPC405CoreIPCoreCustomCoreICONILAILAILAIBACustomLogic