EDA实验：4-10译码器与7选1选择器设计.pdfVIP

4—10译库ieee；使用

ieee.std_logic_1164.all；实体dec10

是端口(a3,a2,a1,a0,s1,s2,s3:输入

std_logic；y:输出std_logic_

vector(9downto0));

enddec10;architectureoneof

dec10issignal

a:std_logic_vector(3downto0);

signals:std_logic_vector(0to2);

signald:std_logic_vector(6

downto0);beginaa3a2a1

a0;ss1s2s3;das;y

1111111110whend0000100else

1111111101whend0001100else

1111111011whend0010100else

1111110111whend0011100else

1111101111whend0100100else

1111011111whend0101100else

1110111111whend0110100else

110