数字集成电路设计：第16讲-电路陷阱与变化因素.pptx

Lecture16:

CircuitPitfalls

16:CircuitPitfalls2OutlineVariationNoiseBudgetsReliabilityCircuitPitfalls

16:CircuitPitfalls3VariationProcessThresholdChannellengthInterconnectdimensionsEnvironmentVoltageTemperatureAging/Wearout

16:CircuitPitfalls4ProcessVariationThresholdVoltageDependsonplacementofdopantsinchannelStandarddeviationinverselyproportionaltochannelareaChannelLengthSystematicacross-chiplinewidthvariation(ACLV)Randomlineedgeroughness(LER)InterconnectEtchingvariationsaffectw,s,h[Bernstein06]CourtesyTexasInstrumentsCourtesyLarryPileggi

16:Circ