数字集成电路设计:第12讲-可测试性设计.pptx

数字集成电路设计:第12讲-可测试性设计.pptx

Lecture12:

DesignforTestability

12:DesignforTestability2OutlineTestingLogicVerificationSiliconDebugManufacturingTestFaultModelsObservabilityandControllabilityDesignforTestScanBISTBoundaryScan

12:DesignforTestability3TestingTestingisoneofthemostexpensivepartsofchipsLogicverificationaccountsfor50%ofdesigneffortformanychipsDebugtimeafterfabricationhasenormousopportunitycostShippingdefectivepartscansinkacompanyExample:IntelFDIVbug(1994)Logicerrornotcaughtuntil1MunitsshippedRecallcost$450M(!!!)

12:DesignforTestability4LogicVerif

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