【精品】lab5.pdfVIP

Multi-Rate Systems Multi-Rate Systems Introduction In this lab you will be exploring the effects of the rate changing blocks available in System Generator including the Upsample, Downsample, Serial to Parallel and Parallel to Serial blocks Note: There is a completed example in lab5/solutions folder Objectives After completing this lab, you will be able to: • Change the sample rates in a DSP System • Convert a serial stream of data to a parallel word • Convert a parallel word of data into a serial stream Lab Setup The following software is required to be installed on your system to successfully complete this lab 1. System Generator 8.2 2. ISE 8.2.01 3. ISE CORE Generator IP Update 1 4. MATLAB / Simulink R2006a Creating a 12 x 8 MAC 05b-3 Using the Xilinx System Generator 1-877-XLX-CLAS Procedure 1. Launch the MATLAB program and once invoked change directory to: C:\SysGen_Training_Labs\lab4 2. Open up a new Simulink diagram and create the simple diagram shown in Figure 1. Use the “Counter Limited” block from the Simulink/Sources library and set the upper limit of the counter to 10. Set the quantization of the Gateway In block to “fix [8 0] Figure 1 – Simple Counter example 3. Simulate the counter for 10 simulation cycles and observe the results. Figure 2 – Output values from the Counter Limited 4. Add a Downsample Block form the Xilinx Blockset/Index library between the Gateway In /Gateway Out blocks and resimulate the design. What do you observe? Figure 3 – Simple counter with Downsamp