LTE Turbo码QPP交织地址并行计算算法与硬件实现.doc

  LTE Turbo 码 QPP 交织地址并行计算算法 与硬件实现 詹仙宁，别志松** 5 10 （北京邮电大学信息与通信工程学院，北京 100876） 摘要：Turbo 码是目前性能最好的信道编码之一。LTE Turbo 码由于采用 QPP 无冲突交织器 作为其内交织器，可以方便地进行交织地址的高速并行实时计算，因此十分有利于译码器的 并行高速实现。本文首先分析了 QPP 交织器的特点并讨论了按子块划分时交织地址并行计 算的一种方法，接着提出了一种实现简单的可实时并行计算交织地址的算法及其对应的 FPGA 实现电路。本文所设计的计算算法与电路无需外部存储器存储大量的交织地址，具有 实现复杂度低、关键路径延迟小、参数灵活可配等特点，完全可以应用于 LTE Turbo 码以及 其他采用 QPP 交织器的 Turbo 码高速并行译码器的硬件设计中。 关键词：信道编码；Turbo 码；QPP 交织器； 交织地址并行计算算法；电路设计 中图分类号：TN92 15 Parallel Computation Algorithm and Hardware Implementation of LTE Turbo Codes QPP Interleaving Address Zhan Xianning, Bie Zhisong 20 25 30 (School of Telecommunication and Information Engineer, Beijing University of Posts and Communications, Beijing 100876) Abstract: Turbo code is one of the best channel encoding codes. LTE Turbo Codes use QPP conflict-free interleaver as the inside interleaver and can be easily implemented to calculate the parallel interleaver address in real-time and is really suitable for high-throughput parallel Turbo decoder design. In this paper, we firstly analyze the characteristic of QPP interleaver and discuzz the method to calculate the interleaver address parallelly in a parallel decoding scheme. An algorithm with low complexity and its corresponding FPGA implementation circuit architecture are proposed to compute the interleaver address in real-time parallelly. The algorithm and circuit need no extra storing resources to store the massive interleaver address, and are easy for implementation with low path delay and flexible parameter configuration. The proposed algorithm and circuit can be widely used in the parallel decoder design for LTE Turbo codes and any other Turbo codes with QPP interleaver. Key words: Channel Encoding Codes; Turbo codes; QPP interleaver; interleaver address computation algorithm; circuit design 35 0 引言 Turbo 码[1]很好的应用了香农信道编码定理中的随机性编译码条件和最大似然译码方 案，因此成为迄今为止最接近香农极限的信道编码方式之一。其中，随机性编译码是通过将 待编码比特序列经过交织器交织置乱的方式来实现的。Turbo 码交织器的交织特性是影响其 40 译码性能的关键因素之一。Turbo 码中的交织器可以使生成码字码重较小的比特序列经过交 织