【毕业论文】数字化频率测试系统的电路设计.doc

数字化频率测试系统的电路设计 ——硬件部分的设计 摘要 本文介绍了用可编程逻辑器件设计简单频率计的实现过程。利用美国Altera公司的MAX+PLUS软件,以原理图输入方式设计了一个频率计,下载到CPLD的模型机,经仿真检验测频范围可达1Hz～10KHz,用6位LED扫描显示电路。体现了可编程逻辑器件电路设计的更趋合理，降低了硬件电路的设计难度以及原理图设计方法的直观性和易用性的特点。产品的质量得到了提高．传统的方法设计这两个芯片是可能需要若干个芯片互连起来，这样就带来了系统的不稳定性，而利用本文的方法只需一片CPLD或FPGA芯片就能完成，这就减少了系统的不稳定因素，并且在设计电路板时能够减少电路板的尺寸．另外，由于是单片芯片，没有太多的连线，它的时延是很小的，实时性很强，从上面的仿真结果看，第一个芯片从CLK到Y1和Y2的延时时间仅为6.9ns和7.0ns，第二个芯片从CLK到输出的延时约为6.6ns。 关键词：可编程逻辑器件 简单频率计 硬件电路 Digital Circuit Design Frequency Test Systems —— The Design Of Hardware Hart ABSTRACT Design the realization course of the simple frequency counter with the programmable logic device in introduction to this text. Utilize MAX +PLUS software of U.S.A. Altera Company, has input the way and designed frequency counter with the principle picture, download model machine to get CPLD, is it examine by emulation range can reach 1Hz-10KHz frequently, is it show to in charge of with 6 number to examine. Reflect programmable logic device reasonable , reduce design degree of difficulty , hardware of circuit and principle picture design method and apt to use. The quality of product got exaltation. Traditional method design these two chips may need some chips to connect with each other, so bring the unsteady of the system, but make use of textual method to need one CPLD or FPGA chip can complete, this reduce system of unsteady factor, and while designing circuit board can reduce the size of circuit board, moreover, in view of the fact single slice chip, there are no too many on-lines, its hour postpone is pimping, the solid hour is very strong, imitating from above true result see, the first chip is from CLK to Y1 and Y2 postpone always is only for 6.9 ns and 7.0 ns, the second chip is from CLK to outputs postpone about is a 6.6 ns. Key Word: Programmable Logic Device Simple Frequency Counted. Hardware Circuit 目 录 前言 1 第一章 EDA工具软件的使用方法 2 1．1 MAX+plus II的安装方法 2 1．2原理图输入法的层次化设计 5 1．3 MAx+plus II老式宏函数的应用 6 1．4 MAX+plusII强函数的应用 6 第二章 硬件描