一种具有优良分辨力, 线性及温度稳定性的量化时延的产生方法.docVIP

一种具有优良分辨力、线性及温度稳定性的量化时延的产生方法* 屈八一12，周渭1王海1李智奇1许建华，张超 （1　西安电子科技大学机电工程学院　西安　710071；2　中国空间技术研究院西安分院　西安　710071；3　电子测试技术国家科技重点实验室青岛266555） TM935　　文献标识码：A　　国家标准学科分类代码：460. 4030 Time to digital method with good precision, linearity and temperature stability Qu Bayi1,2, Zhou Wei1, Wang Hai1, Li Zhiqi1, Xu Jianhua3, Zhang Chao3 (1 School of Electro-Mechanical Engineering, Xi’dian University, Xi’an 710071, China ;2 China Academy of Space Technology of Xi’an, Xi’an 710000, China; 3 Electronic Test Measurement Technology National Laboratory, Qingdao 266555, China） Abstract：Time to digital converter (TDC) and time delay element with a resolution better than nanosecond are in great demand in many instruments and measurements at present. Transmission delay and its application in a Time to digital technology (TDT) are studied in this paper. The relationships between resolution, precision, quality and stability are pointed out in theory; and then experiments are carried out to test the analysis result. Experiment results show that the new TDT is better than traditional TDT based on COMS delay element in resolution, precision, stability and manufacturing. Furthermore, a TDC with a resolution better than 300 ps and a digital range better than 2 ns is designed using this technology. The TDC delay accuracy has relationship with the detection circuits used and as high as 12 ps delay accuracy can be achieved when a calibration is carried out. Key words：time-to-digital; CMOS; transmission delay; picosecond 1　引　　言 目前很多领域内需要高分辨率高精度的时间量化技术。产生延迟的通常方法是利用器件对信号的延迟，典型的方法是将很多CMOS门电路顺序连在一起构成一个延迟链，所得延迟链的延迟分辨率为1个CMOS门电路的延迟，一般在ns量级。为了提高延迟分辨率采用了一种时间游标法，为了解决CMOS门电路不可能完全一致及不匹配情况下它的延迟量会变化等问题采用了锁时环技术，经过这些改进后它能获得的分辨率一般为50 ps，好的可达13 ps[1-4]。该技术具有集成度高的优点，不过实现时存在对电路加工工艺要求高的特点，同时如果继续采用该技术提高分辨率就需要进一步提高加工工艺和控制DLL环路的精度，这将会很困难[5-10]。利用电磁信号等在介质中传输时的高准确度、稳定度和高速度等特征可以将长度量转换为时间量来测量，用无线的方法实现的导航和精密定位就是这个原理。本文利用传输介质进行时间量化的可行性及特点等问题进行了理论及实验研究并以此为基础设计了一个分辨率优于300 ps的时间量化仪。 2　传输延迟的特点 21　基于传输线延迟与CMOS门延迟量化的原理是相同的，主要不同是前