基于FP的GA的串口控制器设计中英文翻译.docVIP

英文原文 The serial controller design based on FPGA Introduction The use of hardware description language (HDL) is becoming a more dominant factor, when designing and verifying FPGA designs. The use of behavior level description not only increases the design productivity, but also provides unique advantages in the design verification. The most dominant HDL stoday are called Verilog and VHDL. This application note will illustrate the use of Verilog in design and verification of a digital UART (Universal Asynchronous Receiver Transmitter). Defining the UART. The UART consists of two independent HDL