基于Verilog HDL语言的串口设计.docxVIP

基于Verilog HDL语言的串口设计串口Verilog HDL代码：//串口module trans(clk,rst,en,TxD_data,Wsec,RxD,TxD,TxD_busy,rcven,RxD_data);//时钟50MHzinput clk,rst,en;//en时发送数据使能input [7:0]TxD_data;//发送数据输入input [2:0]Wsec;//波特率调节0-2400；1-4800；2-9600；3-14400；4-19200；5-38400；6-115200；7-128000input RxD;//接收数据输入端output TxD,TxD_busy,rcven;//发送，发送忙，接收结束标志输出output [7:0]RxD_data;//接收数据输出wire Baud1,Baud8;reg [7:0]addwire;//RAM地址连线reg [7:0]data;wire[7:0]AD_t;//读取RAM数据的地址用于发送wire[7:0]AD_r;//接收的数据存储在RAM中的地址wire [7:0]datawire;//数据连线//发送例化trans_t tt1(.clk_t(clk),.rst_t(rst),.en_t(en),.BTI_t(Baud1),.recen(recen),.TxD_data_t(datawire),.TxD_t(TxD),.addro_t(AD_t),.TxD_busy_t(TxD_busy));//波特生成例化BaudG tt2(.clk_b(clk),.rst_b(rst),.BTO_b(Baud1),.BTO_R(Baud8),.Wsec_b(Wsec));//接收例化trans_r tt3(.clk_r(clk),.rst_r(rst),.BTI_r(Baud8),.RxD_r(RxD),.RxD_data_r(RxD_data),.wren_r(wren_r),.addro_r(AD_r),.RxD_end(RxD_end));//LPM_RAM例化RAM0 tt4(.address(addwire),.clock(~clk),.data(data),.wren(wren_r),.q(datawire));always @(posedge clk or negedge rst) if(~rst)addwire = 8else if(RxD_end)beginaddwire =AD_r ;data=RxD_data;endelse addwire=AD_t;endmodule //发送模块module trans_t(clk_t,rst_t,en_t,BTI_t,TxD_data_t,TxD_t,recen,TxD_busy_t,addro_t,recen );input clk_t,rst_t,en_t,BTI_t;input [7:0]TxD_data_t;output TxD_t;output TxD_busy_t;output recen;output [7:0]addro_t;reg TxD_t;reg [7:0]TxD_dataReg;//寄存器reg [7:0]addro_t;//reg [3:0]state;reg recen;wire TxD_busy_t;assign BaudTick = BTI_t;//波特输出// 发送启动wire TxD_ready = (state==0); // TxD_ready = 1assign TxD_busy_t = ~TxD_ready; // 加载发送数据always @(posedge clk_t or negedge rst_t) if(~rst_t)TxD_dataReg = 8else if(TxD_ready en_t)TxD_dataReg = TxD_data_t;// 状态机发送always @(posedge clk_t or negedge rst_t)if(~rst_t) beginstate = 4b0000; // 复位时发送1TxD_t = 1b1;endelsecase(state)4b0000: if(en_t ) beginstate = 4b0100; // 检测发送开始end4b0100: if(BaudTick en_t) beginstate = 4b1000; // 发送起始位0TxD_t = 1b0;end4b1000: if(BaudTick en_t) beginstate = 4b1001; // bit 0if(en_t)TxD_t = TxD_dataReg[0];else