四选一多路选择器的VHLD语言程序设计.docVIP

一、四选一多路选择器 1、选择信号赋值语句 library ieee; use ieee.std_logic_1164.all; entity mux4 is port(d0,d1,d2,d3:in std_logic_vector(3 downto 0); sel:in std_logic_vector(1 downto 0); y:out std_logic_vector(3 downto 0)); end; architecture halarch of mux4 is begin with sel select y=d0 when 00, d1 when 01, d2 when 10, d3 when others; end; 2、case语句 library ieee; use ieee.std_logic_1164.all; entity mux4_1 is port(d0,d1,d2,d3:in std_logic_vector(3 downto 0); sel:in std_logic_vector(1 downto 0); y:out std_logic_vector(3 downto 0)); end; architecture halarch of mux4_1 is begin