四选一多路选择器的VHLD语言程序设计.doc

一、四选一多路选择器 1、选择信号赋值语句 library ieee; use ieee.std_logic_1164.all; entity mux4 is port(d0,d1,d2,d3:in std_logic_vector(3 downto 0); sel:in std_logic_vector(1 downto 0); y:out std_logic_vector(3 downto 0)); end; architecture halarch of mux4 is begin with sel select y=d0 when 00, d1 when 01, d2 when 10, d3 when others; end; 2、case语句 library ieee; use ieee.std_logic_1164.all; entity mux4_1 is port(d0,d1,d2,d3:in std_logic_vector(3 downto 0); sel:in std_logic_vector(1 downto 0); y:out std_logic_vector(3 downto 0)); end; architecture halarch of mux4_1 is begin case sel is when 00= y =d0; when 01= y =d1; when 10= y=d2; when others=y=d3; end case; end; 3、if语句 library ieee; use ieee.std_logic_1164.all; entity mux4_3 is port(d0,d1,d2,d3:in std_logic_vector(3 downto 0); sel:in std_logic_vector(1 downto 0); y:out std_logic_vector(3 downto 0)); end; architecture halarch of mux4_3 is begin process(d0,d1,d2,d3,sel) begin if(sel=00)then y=d0; elsif(sel=01)then y=d1; elsif(sel=10)then y=d2; else y=d3; end if; end process; end halarch; 二、三人表决器 library ieee; use ieee.std_logic_1164.all; entity decision is port(n:in std_logic_vector(2 downto 0); f:out std_logic); end; architecture dec of decision is begin process(n) variable n0_n1,n1_n2,n0_n2:std_logic; begin n0_n1:=n(0) and n(1); n1_n2:=n(1) and n(2); n0_n2:=n(0) and n(2); f=n0_n1 or n1_n2 or n0_n2; end process; end dec;