数字集成电路分析和设计-第一章答案.docVIP

To express each equation as sum-of-product and as a product-of-sum first write the truth table then create a Karnaugh map from the truth table. Then use the 1’s for sum-of products and 0’s for product of sums. A B C F 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 Table P 1 C AB 00 01 11 10 0 0 0 1 0 1 0 1 1 1 Table P 2 Collecting the terms together we find: D AC 00 01 11 10 0 0 0 1 1 1 1 1 0 0 Table P 3 Collecting the terms together we find: There are many ways to do the circuit, here’s one version. First create a truth table. A B C F 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Table P 3 The Boolean equation is: . All NAND circuit (yours may be slightly different) is shown below: All NOR circuit: There are many ways to do the circuits, here’s one version. See solution to P1.2 for guidance. Implementing the truth table into K-Map form: AB 00 01 11 10 Sum 0 1 0 1 Carry 0 0 1 0 Table P 4 the resulting Boolean equations are: The associated gate equivalent will be: Figure P 1 First, the full adder truth table: A B CIN COUT Sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 Table P 5 Implementing the truth table into K-Map form: A BCIN 00 01 11 10 0 0 1 0 1 1 1 0 1 0 Table P 6: Sum K-Map A BCIN 00 01 11 10 0 0 0 1 0 1 0 1 1 1 Table P 7: COUT K-Map The associated gate equivalent is straight-forward based on the previous problems. This question is as easy as it looks, no tricks here. The delay from ‘a’ to ‘b’ is simply the delay of an inverter times the number of inverters which would be 10 ns. The period in this case is simply twice the delay around the loop, T=20 ns. The frequency is 1/T =50 MHz. The delay of an RC circuit with a step input applied is: In our case, we are solving for t: For V(t)=0.6V: 1.2V: This circuit will never read 1.2V. The delay from 10% to 90% VDD: The delay for a and b uses the exponential rise/fall equation: For RDOWN: For RUP: