高频传输理论.pdfVIP

Introduction of High-Speed Introduction of High-Speed Transmission Line Theory Transmission Line Theory (高頻傳輸線理論簡介) (高頻傳輸線理論簡介) What’s “High Speed”? • Rise Time ~2 nsec • Clock Period ~30 nsec • Clock frequency ~33 MHz • v = f λ( 傳播速度=頻率*波長) ，當待測物符合以㆘ 的條件 待測物長度 ≧ 1 你想要輸入待測物內信號之波長 20 那麼這個輸入信號與這個待測物之間的關係就是屬 於高頻範圍，所測到的各種參數就是高頻參數。(註: ㈲些參考書籍是與1/10~1/20的波長) Features of a Digital Signal in the Time Domain Features: Rise time: • Voltage • 0% - 100% • Clock Period • 10% - 90% • Clock Frequency • 20% - 80% • Rise time Rise Time and Clock Frequency • As clock frequency increases, Clock period decreases. T =1/F period clock As clock period decreases, the rise time of all signals usually must decrease. • Typical timing budget allocation is T =15 ＊t period rise time • trise time = 0.35 / BW (Bandwidth) BW = 0.35 / t rise time Bandwidth (BM, 頻寬) • Bandwidth : the highest frequency that is significant 簡言之, 能確保訊號不變的最高頻率 • ㆒般而言, BW = 5 * clock frequency Example: 133 MHz PC = BW 660 MHz • 對 IC package, connector cable, 決定 BW是根據時 脈(clock) 信號的 risetime, 而非clock frequency. • BW愈大, ㈹表更高頻訊號成份可以存在, 使㆒個脈 波(pulse)訊號更接近方波(risetime short) • BW愈大的傳輸線, 可承載較高頻訊問, ㈲更高的㈾ 料傳送. How Packaging and Interconnect Affect System Performance? Timing Budget: 1. Gate delay, Driver delay, setup time, hold time, packaging delays, wiring delays 2. Clock skew 3. Rise