EDA技术及应用教程 教学课件 作者 赵全利 EDA 实例源程序代码.docVIP

第4章 用VHDL程序实现常用逻辑电路 4.1 组合逻辑电路设计 4.1.1 基本逻辑门 library ieee; use iee.std_logic_1164.all; entity jbm is port(a,b: in bit; f1,f2,f3,f4,f5,f: out bit); end jbm; architecture a of jbm is begin f1=a and b; --构成与门 f2=a or b; --构成或门 f=not a; --构成非门 f3=a nand b; --构成与非门 f4=a nor b; --构成异或门 f5=not(a xor b); --构成异或非门即同门 end; 4.1.2 三态门 library ieee; use ieee.std_logic_1164.all; entity tri_s is port(enable: in std_logic; datain: in std_logic_vector(7 downto 0); dataout: out std_logic_vector(7 downto0)); end tri_s; architecture bhv of tri_s is begin process(enable,datain) begin if enable=1 then dataout=datain; else dataout=ZZZZZZZZ; end if; end process; end bhv; 4.1.3 3-8译码器 library ieee; use ieee.std_logic_1164.all; entity decoder3_8 is port(a,b,c,g1,g2a,g2b: in std_logic; y: out std_logic_vector(7 downto 0)); end decoder3_8; architecture a of decoder3_8 is signal dz:std_logic_vector(2 downto 0); begin dz=cba; process (dz,g1,g2a,g2b) begin if(g1=1and g2a=0and g2b=0)then case dz is when 000= y when 001= y when 010= y when 011= y when 100= y when 101= y when 110= y when 111= y when others=y=XXXXXXXX; end case; else y end if; end process; 4.1.4 优先编码器 library ieee; use ieee.std_logic_1164.all entity coder is port(din: in std_logic_vector(0 to 7); output: out std_logic_vector(0 to 2)); end coder; architecture behave of coder is signal sint: std_logic_vevtor(4 downto 0); begin process(din) begin if (din(7)=0) then output = 000 ; elsif (din(6)=0) then output = 100 ; elsif (din(5)=0) then output = 010 ; elsif (din(4)=0) then output = 110 ; elsif (din(3)=0) then output = 001 ; el