数字电子技术基础 教学课件 作者 赵莹CH6 CH6.7.pptVIP

时序逻辑电路 6.7用VHDL语言描述时序逻辑电路 6.7.1移位寄存器的VHDL描述 4位双向移位寄存器74LS194的VHDL描述 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY HC194 IS PORT(D :IN STD_LOGIC_VECTOR(0 TO 3); CR,SR,SL,S1,S0:IN STD_LOGIC; CP:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(0 TO 3));END HC194;ARCHITECTURE ONE OF HC194 IS SIGNAL PCX:STD_LOGIC_VECTOR(0 TO 3); BEGIN PROCESS(CR,CP) BEGIN IF(CR=’0’) THEN PCX=0000; ELSE IF(cp’ EVENT)AND(CP=’1’) THEN IF((s1=0) AND (s0=’1’)) THEN  PCX(0)=SR;