EDA技术P5-VHDL行为与结构描述_课测2~3.pptVIP

课堂测试2 采用元件例化，调用4位全加器，设计8位全加器， 4位全加器实体说明如下： 课堂测试2-参考答案 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY adder8 IS PORT ( x, y : IN STD_LOGIC_VECTOR (7 DOWNTO 0); Cin : IN STD_LOGIC; Sum : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); cout : OUT STD_LOGIC ); END ENTITY adder8; ARCHITECTURE structural OF adder8 IS COMPONENT adder IS PORT ( x, y : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Cin : IN STD_LOGIC; Sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); Cout : OUT STD_LOGIC ); END COMPONENT; SIGNAL carry: STD_LOGIC; BEGIN c0: adder PORT MAP ( x =x ( 3 downto 0), y = y (3 downto 0), cin = Cin, sum=Sum(3 downto 0), Cout = carry ); c1: adder PORT MAP ( x =x ( 7 downto 4), y = y (7 downto 4), cin = carry, sum=Sum(7 downto 4), Cout = Cout ); END ARCHITECTURE structural; 课堂测试3 设计一个4位计数器 课堂测试3-参考答案 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY counter4 IS PORT ( CLK : IN STD_LOGIC; Cout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END ENTITY counter4; ARCHITECTURE rtl OF counter4 IS SIGNAL Ctr_in4 : STD_LOGIC_VECTOR (3 DOWNTO 0) := “0000”; BEGIN CTR_P: Process(CLK) Begin If CLK’event and CLK = ‘1’ then Ctr_in4 = Ctr_in4 + ‘1’; End if; End process; Cout = Ctr_in4; END ARCHITECTURE structural; * * LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY adder IS PORT ( x, y: IN STD_LOGIC_VECTOR(3 DOWNTO 0); cin: IN STD_LOGIC; sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cout: OUT STD_LOGIC); END ENTITY adder; 8 8 4 4 4 4 x x x y y y Cin Cin Cin Cuot Cuot Cuot 8 8 4 4 4 4 x x x y y y Cin Cin Cin Cuot Cuot Cuot 利用进程语句和时钟信号描述 *