直流电机的控制vhdl.docVIP

VHDL设计举例：直流电机控制器 /html/EDAjishu/2006/0817/340.html LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; ENTITY dccount IS port ( clk : IN STD_LOGIC; AI : IN STD_LOGIC_VECTOR(3 DOWNTO 0); CO : out STD_LOGIC_VECTOR(3 DOWNTO 0); pulse: IN STD_LOGIC; driverA,driverB: OUT STD_LOGIC; S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); P : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); sp : out STD_LOGIC); END dccount; ARCHITECTURE a OF dccount IS SIGNAL f: STD_LOGIC_VECTOR(5 downto 0); SIGNAL f_hz: STD_LOGIC; SIGNAL OSC: STD_LOGIC; SIGNAL OSC1: STD_LOGIC; SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL A: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CODE: STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL bcd:STD_LOGIC_VECTOR(23 downto 0); SIGNAL COUNT:STD_LOGIC_VECTOR(23 downto 0); SIGNAL SUM: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL D: STD_LOGIC_VECTOR(3 DOWNTO 0):=0000; SIGNAL ind_coil: STD_LOGIC_VECTOR(3 downto 0) := 0001; SIGNAL Hz:STD_LOGIC; SIGNAL spo: STD_LOGIC; SIGNAL SW:STD_LOGIC; SIGNAL KEY:STD_LOGIC; SIGNAL DRA,DRB:STD_LOGIC; BEGIN DRIVERA=DRA; DRIVERB=DRB; p(5 downto 0) = f(5 downto 0); CO(3 DOWNTO 0) =C(3 DOWNTO 0); A (3 DOWNTO 0)=AI(3 DOWNTO 0); SP=SPO; -----------------div------------------------ PROCESS(OSC) VARIABLE d_ff: STD_LOGIC_VECTOR(20 downto 0); VARIABLE DELAY: STD_LOGIC_VECTOR(23 DOWNTO 0); BEGIN WAIT UNTIL clk = 1; IF d_ff(20 downto 0) = 2E6 THEN d_ff(20 downto 0) := 000000000000000000000; ELSE d_ff(20 downto 0) := d_ff + 1; END IF; f_hz = not d_ff(6); OSC = not d_ff(10); OSC1 = not d_ff(17); IF DELAY=500000 THEN DELAY:=000000000000000000000000;HZ=NOT Hz; ELSE DELAY:=DELAY+1; END IF; END PROCESS ; ---------------------------------------------- PROCESS (F_HZ,OSC,OSC1,HZ,PULSE) VARIABLE B: