基于FPGA的参数化时域脉冲压缩IP核的设计.pdfVIP

2 Vol. 4 No . 2 2006 4 Radar S cience and Tec hnology April 2006 * FPGA IP , , ( , 230031) : 数字脉冲压缩技术在现代雷达中已得到广泛应用, 但不同雷达的参数各不相同, 脉压处理电 也各不相同, 因而使脉压电 的通用性甚差该文介绍了一种基于现场可编程门阵列( FPGA) 的参数化 时域脉冲压缩IP 核的设计方法用该方法设计的脉冲压缩IP 核通过参数化方式,使电 能适应脉冲压缩 工作模式数最大处理点数输入数据率数据/ 系数的宽度乘法器流水级数及各种工作模式的对称性的改 变, 从而使脉压电 的通用性大为增强 : 时域脉冲压缩; 参数化设计; 现场可编程门阵列; IP 核 :T N957; T N78 :A : 1672-2337( 2006) 02-0094-04 Design of Parameterized IP CoreforTime-Domain Pulse Compression Based on FPGA ZH U De-z i, LU O C uan- ui, WANG Q-i z i (E ast China Resear ch Institute of Electronic E ngineer ing , H ef e i 230031, China) Abstract: As well known, pulse compression is w idely used to modern radars. For different radars, t e parameters are different. It makes t e pulse compression circuits be not universal. T is paper introduces a met od t o design based on FPGA parameterized IP cores for time-domain pulse compression. In design of radar system, we can finis designing of t e module for pulse compression wit t e IP core quickly. Key ords: time-domain pulse compression; parameterized design; FPGA; IP core , [ 1] 1 so = si * h ( 1) sih so ( DPC) () , * , , ( 1) , N- 1 N- 1 ,