VHDL编写的基本元件程序.docVIP

VHDL语言设计 与门： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY AN IS PORT ( A,B: IN STD_LOGIC ; Y : OUT STD_LOGIC ); END ENTITY AN; ARCHITECTURE AC OF AN IS BEGIN Y=A AND B; END ARCHITECTURE AC; 或门： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY BN IS PORT ( A,B: IN STD_LOGIC ; Y : OUT STD_LOGIC ); END ENTITY BN; ARCHITECTURE BC OF BN IS BEGIN Y=A OR B; END ARCHITECTURE BC; 非门： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY DN IS PORT ( B: IN STD_LOGIC ; Y : OUT STD_LOG