有关综合性实验(EDA).pptVIP

* 表1 存储控制器真值表 0 1 读（READ） 1 0 写（WRITE） 0 0 判断（DECISION） 0 0 空闲（IDLE） WE OE 输出 状态 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY moore IS PORT(clk,ready,read_write: IN Std_Logic; oe,we : OUT Std_Logic); END moore; ARCHITECTURE state_machine OF Moore IS TYPE state_type IS (idle,decision,read,write); SIGNAL present_state,next_state: state_type; BEGIN state_comb: PROCESS(present_state,ready,read_write) BEGIN CASE present_state IS WHEN idle = oe=0; we=0; IF(ready=1) THEN next_state=decision; E