SIGGSP Low-Power Circuit Techniques for iSensors.docVIP

SIGGSP: Low-Power Circuit Techniques for iSensors Monthly Report (October 7, 2013) Team Members NTU PI: Tsung-Hsien Lin Students: Chang-Hsiang Weng (PhD), Tzu-An Wei (MS), Yi-Chu Chen (MS) Intel Champions: Chang-Tsung Fu and Erkan Alpman Discussion with Intel Champions Conference calls on Sep. 27, 2013, 8:30 ~ 9:30 AM, Taipei time. Discussion topics: (1) investigate the technique of dynamic element matching; (2) chip measurement preparation; (3) discuss wireless transmitter architectures (Cartesian, Polar, Outpahsing) and non-linear type power amplifier for WLAN application; (4) introduce inverse Class-D power amplifier for outphasing architecture. Progress Since there is no shaping for feedback signal, the non-linearity of a multi-bit DAC will induce harmonic tones. Here, we use DAC with 1% gradient variation to model the mismatch; the simulation results are shown in Figure 1. The purple line is without DAC mismatch (ideal case). When DAC mismatch is added, not only the harmonic tones but also the in-band noise floor is increased. After applying the data-weighted-averaging (DWA), the harmonic tones and the noise floor is reduced. From the result, we can conclude that applying the DWA can help to increase not only SNDR but also SNR considering the mismatch of DAC. Figure 1. The effect of DAC mismatch and DWA We have completed the PCB layout and its implementation as shown in the Figure 2. The chip is packaged with 48 pins. Figure 2. PCB implementation for CTDSM chip testing Inverse Class-D power amplifier has zero voltage switching (ZVS) feature, less passive components, inherent differential, compared to the conventional Class-D, the Class-E, the Class-F power amplifier. Furthermore, the inverse Class-D is also suitable for power combination to implement high output power with high efficiency transmitter for wireless applications. Figure 3. (a) Inverse Class-D power amplifier; (b) Inverse Class-D power amplifier with transformer-based power combiner. Bri