Verilog语言及应用技术1.pdfVIP

Verilog语言及应用技术 Syllabus English COURSE: everything is in English Course Description: This is an advanced digital system design course based on hardware programming language – Verilog HDL. Course Objectives: 1. To get familiar with the philosophy and methodology of the digital system design. 2. To have a hands-on knowledge of Verilog HDL Syllabus Time and Location: Class: weeks 3-10 Monday: 10:10-12:00 大成204 Wednesday: 10:10-12:00大成204 Labs: 4 Lab Assignments, TBD Instructor: Professor Jie Yang (杨杰） Email: yangjie@ise.neu.edu.cn Cell phone: Office: 415 Office Hours: by appointment Syllabus Textbook: Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall, 2003 References: 1. Jayaram Bhasker, Verilog HDL synthesis: a practical primer, Star Galaxy Pub., 1998 2. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, 2nd Ed., Pearson Education,2005. 3. Stephen Brown Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, Tata McGraw-Hill, 2002. Simulation Software: ModelSim PE student edition Syllabus GRADING: Homework: 20%, Quiz: 20%, Lab: 25%, Exam: 35% CHEATING POLICY : Academic integrity is very important. First–time offender will get 0 point in the corresponding assignment. Cheating twice will result in a course grade of “Fail” Typical examples of cheating are copying homework/lab assignments/exam problems from another student, or allowing them to be copied. Syllabus Contents to be covered in this Course: 1. Introduction to digital design methodology 2. Review of Boolean Algebra and Digital Logic Basics 3. Combinational logic design 4. Sequential logic design 5. Logic Design with Verilog 6. Behavioral Mode