基于VHDL硬件描述语言FPGA新实验开发--简易处理器实现.pdfVIP

基于VHDL硬件描述语言的FPGA新实验开发 ——简易处理器实现 陆玲霞，姚维，高健 浙江大学 电气工程学院,浙江杭州 310027 E-mail:lulingxia@zju.edu.cnyaowei@zju.edu.cngaojian@zju.edu.cn 摘 要 针对FPGA课程实践性强、设计性要求高的特点，通过引入暑期短学期集中培训的方式，尽量压缩理论课堂教学 时间，充分给予学生实验室动手实践机会，同时结合项目给定的方式开展实验课堂教学，并通过结果和过程两者相结合的 评定方式，充分调动学生学习的积极性。实验过程中通过采用VHDL硬件描述语言实现能够执行相应指令的MC 内核等 新实验开发，帮助学生深刻理解微处理器内部结构，特别是让其明白单片机整个系统的核心是一个由系统时钟驱动的全局 状态机的逻辑过程。结果表明：该实验的展开使学生更好的掌握FPGA 的设计原理、步骤和方法，精通VHDL硬件描述语 言的开发和实践，和深刻理解汇编指令的执行过程。 FPGA VHDL MC 关键词 ， ， 处理器，新实验开发人才培养 ThenewexperimentaldevelopmentofFPGAusingVHDL language-simpleprocessorrealization L Lingxia,YAOWei,GAOJian CollegeofElectricalEngineering,ZhejiangUniversity,Hangzhou310027,China E-mail:lulingxia@zju.edu.cnyaowei@zju.edu.cngaojian@zju.edu.cn Abstract:Aimed atthecharacteristicsofstrongpracticality andhighdesignrequirementsofFPGAcourses,andalsoinorder to fullymobilize studentslearningenthusiasminFPGAarea,itintroduced afocustrainingway in shortsummer semester， withcompressingthetheoreticalclassroomtimeandfullygiventhestudentshands-onopportunitiesinlaboratory,atthesame time, combined with the project given way to carry out the experimental teaching, and through the evaluation methods of combination with both outcome and process. During the experiment, in order to help students a deep understanding of the internalstructureofthemicroprocessorandespeciallymakethemunderstandthemicrocontrollercoreofthewholesystemisa logical process of the global state machine driven by the system clock, so a new experiment to be able to perform the correspondinginstructions ofMC corebyusingVHDLlanguagewas introduced.It turns outthat theundertaking ofthese experimentscanmake studentsknowthedesig