VHDL数据类型(vhdl语法).ppt

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity full_bit_adder is port(a,b,ci:in std_logic; y,cout:out std_logic); end full_bit_adder; architecture bh1 of full_bit_adder is begin y = ((not a)and (not b)and ci) or ((not a)and (b) and (not ci)) or ((a)and (not b)and(not ci)) or ((a) and (b)and(ci)); cout = (b and ci) or (a and ci) or (a and b); end bh1; architecture bh2 of full_bit_adder is begin y = a xor b xor ci; cout = (a and b) or (a and ci) or (b and ci); end bh2; configuration con1 of full_bit_adder is for bh2 end for; end con1; （1）触发器设计 D Q CP CP D Q 无上升沿 X Qn-1 0-1 0 0 0-1 1 1 D触发器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff IS PORT( cp,d: IN STD_LOGIC; q: OUT STD_LOGIC); END dff; ARCHITECTURE a OF dff IS BEGIN process(cp) begin if cpevent and cp=1 then q=d; end if; end process; END a; (3) 计数器设计 计 数 器 CLK Q LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; USE ieee.std_logic_arith.ALL; ENTITY counter IS PORT( clk: in STD_LOGIC; q: buffer STD_LOGIC_vector(3 downto 0)); END counter; ARCHITECTURE a OF counter IS BEGIN process(clk) begin if (clkevent and clk=1) then q=q+1; end if; end process; END a; 无控制端四位加计数器 ARCHITECTURE a OF counter IS BEGIN process(clk) begin if (clkevent and clk=1) then if(q9) then q=q+1; else q=0000; -- q=(others=’0’); end if; end if; end process; END a; 无控制端10进制计数器 ‘U’ 未初始化 用于仿真 ’X’ 强未知 用于仿真 ’0’ 强0 用于综合与仿真 ’1’ 强1 用于综合与仿真 ’Z’ 高阻 用于综合与仿真 ’W’ 弱未知 用于仿真 ’L’ 弱0 用于综合与仿真 ’H’ 弱1 用于综合与仿真 ’_’ 忽略 用于综合与仿真 * * VHDL数据类型 FPGA应用技术 二、VHDL数据类型与数据对象 在VHDL程序中，我们经常会遇到这样的语句： Signal A : std_logic; Variable B : std_logic_vector(7 down