基于Petri网与遗传算法的半导体生产线建模与优化调度_曹政才.pdf

2 　　　　　　 Vol.38　No.2 　2010 2 ACTA ELECTRONICA SINICA Feb.　2010 　 Petri 1 2 2 曹政才, 余红霞, 乔　非 (1., 100029;2.CIMS , 201804) 　　　:　、, Petri ., , 、 , .、、 , ., , , . :　;Petri ;;; :　TP273　　　:　A　　　:　0372-2112 (2010)02-0340-05 Petri-Net and GA-Based Approach to Modeling and Optimize for Semiconductor Wafer Fabrication 1 2 2 CAO Zheng-cai , YU Hong-ia , QIAO Fei (1.College of Inf ormation Science and Technology , Beij ing University of Chemical Technology , B eij ing 100029, China; 2.CIMS R esearch Center, Tongji University , Shanghai 201804, China ) Abstract:　As scheduling in semiconductor wafer fabrication is complicated and difficult to optimize, a genetic algorithm (GA)embedded search strategy over a Hierarchical colored timed Petri net (HCTPN)for semiconductor wafer fabrication is pro- posed.All possiblebehaviors of the semiconductor wafer fabrication systems such as lot routing, resourcerestrict, equipment mainte- nance, priority of the system can described through the HCTPN model, which is modeled by hierarchical theory and top-view method.The chromosome representation of the search nodes in GA is record theinformation about the appropriate scheduling policy such as release policy, equipment selecting rule, batching rule and dispatching rule.According to theresults, using different schedul- ingstrategy to simulate and analyzethe performance.The simulation result has proved that the model is efficient and accurate, and the GA scheduler is validity. Key ords:　semiconductor wafer fabrication;hierar