14332331Computer Architecture and Assembly LanguageSpr.ppt

14:332:331Computer Architecture and Assembly LanguageSpring 2006Week 9Building a Single-Cycle Datapath [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides] Head’s Up This week’s material Building a MIPS single-cycle datapath Reading assignment – PH 5.4 Review: Abstract Implementation View Split memory (Harvard) model - single cycle operation Simplified to contain only the instructions: memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j Sequential components (PC, RegFile, Memory) are edge triggered state elements are written on every clock cycle; if not, need explicit write control signal write occurs only when both the write control is asserted and the clock edge occurs Example Let’s modify the ISA and remove the ability to specify an offset for memory access instructions. Specifically, the load-store instructions would contain only two registers. In other words, all MIPS load-store instructions with offsets would become pseudoinstructions and would be implemented using two instructions: lw $t0, 104($t1) = Example cont’d Creating a Single Datapath from the Parts Assemble the datapath segments from the last lecture, add control lines as needed, and design the control path Fetch, decode and execute each instructions in one clock cycle – single cycle design no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., why we have a separate Instruction Memory and Data Memory) to share datapath elements between two different instruction classes will need multiplexors at the input of the shared elements with control lines to do the selection Cycle time is determined by length of the longest path Fetch, R, and Memory Access Portions Multiplexor Insertion Adding the Branch Portion Adding the Control Selecting the operations to perform (ALU, Register File and Memory read/write) Controlling the flow of d