MIPS Architecture.ppt

MIPS Architecture CPSC 321 Computer Architecture Andreas Klappenecker MIPS Design Paradigms Simplicity favors regularity all instructions single size three register operands in arithmetic instr. keep register fields in the same place Smaller is faster 32 registers Make good compromises large addresses and constants versus unique instruction length Make the common case fast PC-relative addressing for conditional branches Basic Functional Components Control unit Register file Arithmetic logic unit (ALU) Program counter (PC) Memory Instruction register (IR) MIPS R2000 Several firsts: First RISC microprocessor First microprocessor to provide integrated support for instruction data cache First pipelined microprocessor (sustains 1 instruction/clock) Implemented in 1985 125,000 transistors 5-8 MIPS How can we load a 32bit constant? How can we load $s0 with 0000 0000 0011 1101 0000 1001 0000 0000 Load upper 16bits with lui $s0, Ox003d so that $s0 contains 0000 0000 0011 1101 0000 0000 0000 0000 Add immediate 16bit value to complete load addi $s0, $s0, 0x0900 so that $s0 contains value 0000 0000 0011 1101 0000 1001 0000 0000 MIPS Addressing Modes Register addressing Base displacement addressing Immediate addressing PC-relative addressing address is the sum of the PC and a constant in the instruction Pseudo-direct addressing jump address is 26bits of instruction concatenated with upper bits of PC What next? Details of the arithmetic logic unit Chapter 4 Project: Build your own ALU Details of datapath and control Chapter 5 Project: Build your own CPU Pipelining Caching * * Simplified Datapath Diagram Program Counter (PC) Instruction Register Register File ALU Memory Data In Address 4 Rs Rt Rd Control Logic ? $t8 24 $s7 23 $s6 22 $s5 21 $s4 20 $s3 19 $s2 18 $s1 17 $s0 16 $t7 15 $t6 14 $t5 13 $t4 12 $t3 11 $t2 10 $t1 9 $t0 8 $a3 7 $a2 6 $a1 5 $a0 4 $v1 3 $v0 2 $at 1 $zero 0 Number Name Value Registers pass parameters to functions return values from functions $s0-$s7