计算机体系结构5【荐】.pptVIP

Pipelined ProcessorsSima, Fountain and KacsukChapter 5 CSE3304 Major Chapter Goals Basic Concepts Design Space of pipelines Overview of pipelined instruction processing Pipelined execution of integer and boolean instructions Pipelined processing of loads and stores Basic principles of pipelining Each task is subdivided into a number of successive tasks A pipeline stage is associated with each subtask Same time required for each stage Each stage outputs to the input of the next stage Pipeline is clocked synchronously. Implementation of pipeline Requires registers between stages Clocked by clock-edge Some important performance measures Cycle time Time to execute one stage Usually dictates the clock rate e.g. 500 MHz processor has 2 nsec cycle time Latency Time to complete one operation In pipelined machines this is more than one clock cycle e.g. 10 stages of 2 nsec result takes for 20 nsecs Affects data dependencies down stream Some important performance measures ... Repetition rate Shortest time interval between repeats Actually determines the performance of the pipeline Many operation have repeat rates of one cycle Some operations like FPMUL re-use a pipeline stage, so cannot accept a new FPMUL each cycle Variable execution phase Some execution units take multiple cycles Consider Power PC 603 FP Pipeline Performance potential of a pipeline Where R is repetition rate in cycles tc is the cycle time of pipeline PowerPC 603 Some real machines Design decisions - 2 stage pipe Design decisions = 4 stage pipe Design decisions 8 stage pipe Why not deeply pipeline? Not all execute phases are equal! Pipeline stalls Register not ready (define use) Data is not available from memory (load use) Conditional result not ready for branch Bypassing Do not need to write and then read registers Applies to load from cache write to register file (RAW dependency) Can eliminate stall for RAW dependency Without bypass Hardware With Bypass Hardware Dependency Resolution Dependencies can be