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A Memory Management Approach for Efficient Implementation of Multimedia
Kernels on Programmable Architectures*
M. Dasigenis, N. Kroupis, A. Argyriou,
K. Tatas, D. Soudris, A. Thanailakis N. Zervas
VLSI Design and Testing Center, VLSI Design Lab
ECE Dept., Democritus University of Thrace, ECE Dept., University of Patras,
- 67 100 Xanthi, Greece 26500, Patras, Greece
Abstract putation and complex functionality with low power con-
sumption, since power consumption affects the battery ser-
A methodologyfor power optimization of the data mem- vice life and weight, cooling requirements, packaging costs
ory hierarchy and instruction memory, is introduced. The as well as the circuit reliability. There also exists a strong
impact of the methodology on a set of widely used mul- pressure for producers of high-end products to reduce their
timedia application krnels, namely Full Search (FS), Hi- power consumption. For this reasons, power consumption
erarchical Search (HS)),Parallel Hierarchical One Dimen- has emerged as a very significant design constraint, that has
sion Search (PHODS), and Three Step Logarithmic Search to be tackled, especially in the high levels of design, where
(3SLS), is demonstrated. Wefind thepower optimal data the most significant savings can be achieved [I].
memory hierarchy applying the appropriate data-use trans- Generally speaking, two possible impleme
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